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            - Sun Proprietary/Confidential: Internal Use Only -
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                        FIELD INFORMATION NOTICE
               (For Authorized Distribution by SunService)

FIN #: I0880-1

Create Date: Oct/25/02

SunAlert: No

Top FIN/FCO Report: No

Products Reference: UltraSPARC-III Cu Processors

Product Category: Server / Service

Product Affected: 

Systems Affected:
-----------------  
Mkt_ID   Platform   Model   Description         Serial Number
------   --------   -----   -----------         -------------
  -         S8       ALL    Sun Fire 3800             -
  -         S12      ALL    Sun Fire 4800             -
  -	    S12i     ALL    Sun Fire 4810             -
  -         S24      ALL    Sun Fire 6800             -


X-Options Affected:
-------------------
Mkt_ID   Platform    Model     Description       Serial Number
------   --------    -----     -----------       -------------
  -         -          -            -                  -

Parts Affected: 

Part Number               Description                       Model
-----------               -----------                       -----
540-5052-03 (or lower)    ASSY CPU 4PROC USIIIP 900MHZ        -
540-5051-04 (or lower)    ASSY CPU 2PROC USIIIP 900+MHZ       -
540-5267-01		  ASSY CPU 4PROC USIIIP 1050MHZ       -

References: 

BugId:   4705197 - cheetah+ incompatible E$ DIMMS not recognized.

Issue Description: 

Sun Fire 3800/4800/4810/6800 firmware version 5.13.3 enforces a
configuration rule stating that System Boards with Late_Write Ecache
DIMMs cannot be used with UltraSPARC-III+ processors.  After installing
5.13.3, POST will identify and configure the processors, but issue a
warning that the Ecache DIMMs are not compatible with this processor
type.  When firmware version 5.14.0 is released, POST will detect and
fail USIII+ processors if Late_Write Ecache DIMMs are installed on the
System Board.

Sun Fire firmware 5.13.3 is available with patch 112494-06.  Firmware
5.14.0 will be released at some future date.  With the 5.13.3 firmware,
there is no direct impact to customer systems, since only a warning is
issued.  With 5.14.0 firmware, USIII+ processors will be failed and
removed from a domain's configuration.

This issue affects Sun Fire 3800/4800/4810/6800 platforms where USIII+
processors are installed onto System Boards with Late_Write Ecache
DIMMs and where firmware 5.13.3 is installed.  System Boards with
Late_Select Ecache DIMMs are not affected.  USIII processors are also
not affected.

Any System Boards with Late_Write Ecache DIMMs existing in customer
systems are a result of FRU replacements.  No systems have shipped from
Sun Manufacturing with this type of board, and all System Boards are
currently shipping, and being reworked, with the Late_Select Ecache
DIMMs.  There is no part number dash level change which will identify
which type of ECache DIMMs a System Board contains.

To identify USIII+ processors in a domain, do the following:
    
    # prtconf | grep -i ultrasparc
    SUNW,UltraSPARC-III+, instance #0
    SUNW,UltraSPARC-III+, instance #1 
    
NOTE: UltraSPARC-III+ processors are also referred to as UltraSPARC-III Cu.     
   
This issue can be identified by looking at the POST logs for a Sun Fire
domain.  After performing a 'setkeyswitch' command for a domain, POST
detection and reporting will provide the following information:

  v4u-6800b:A> showlogs

    Jul 22 15:02:55 v4u-6800b Domain-A.POST: 
      [ID 184071 local0.warning] {/N0/SB2/P0}  
      WARNING: ECache DIMMs are not compatible with processor type.

  v4u-6800b:A> showb

    Slot     Pwr Component Type         State      Status     Domain
    ----     --- --------------         -----      ------     ------
    /N0/SB2  On  CPU Board V2           Active     Degraded   A
    /N0/IB6  On  PCI I/O Board          Active     Passed     A

  v4u-6800b:A> showcomp sb2

    Component    Status   Pending  POST   Description
    ---------    ------   -------  ----   -----------
    /N0/SB2/P0   enabled     -     fail   UltraSPARC-III+, 900MHz, 8M ECache
    /N0/SB2/P1   enabled     -     pass   UltraSPARC-III+, 900MHz, 8M ECache
    /N0/SB2/P2   enabled     -     pass   UltraSPARC-III+, 900MHz, 8M ECache
    /N0/SB2/P3   enabled     -     pass   UltraSPARC-III+, 900MHz, 8M ECache

Notice from the output above that processor /N0/SB2/P0 generated a
warning message, but has been enabled by POST.  If 5.14.0 firmware had
been installed, the processor would have been disabled.

Root cause of this issue is due to a process error at Sun's repair
vendor in EMEA.  System Boards were incorrectly populated with
Late_Write Ecache DIMMs.  While these DIMMs will function correctly on
the above Sun Fire platforms with USIII+ processors, they will not work
with Sun Fire 12K/15K systems.  Since both platform types use the same
System Boards this is a compatibility issue.

Field stocking locations have been purged of the System Boards with the
Late_Write Ecache DIMMs, and it is estimated that only a very small
number of affected System Board FRUs escaped to customer systems
in the EMEA Geography.

When Sun Fire firmware 5.14.0 is released at a later date, POST
diagnostics will not allow USIII+ processors with incorrect Ecache
DIMMS to be configured into a domain.  Firmware 5.13.3 POST will
provide information only, so that proactive replacement of the System
Board can be scheduled.  This change is being implemented in two stages
to reduce the impact on existing installations.

Implementation: 

---
        |   |   MANDATORY (Fully Proactive)
         ---    
         
  
         ---
        |   |   CONTROLLED PROACTIVE (per Sun Geo Plan) 
         --- 
         
                                
         ---
        | X |   REACTIVE (As Required)
         ---

Corrective Action: 

The following recommendation is provided as a guideline for authorized
Sun Services Field Representatives who may encounter the above
mentioned problem.

When Sun Fire firmware 5.13.3 POST identifies a processor with the
following message:

   "WARNING: ECache DIMMs are not compatible with processor type."

replace the System Board as a proactive maintenance measure to avoid a
failed processor during POST with firmware 5.14.0.

Comments: 

None.

============================================================================

Implementation Footnote: 

i)   In case of MANDATORY FINs, Enterprise Services will attempt to    
     contact all affected customers to recommend implementation of 
     the FIN. 
   
ii)  For CONTROLLED PROACTIVE FINs, Enterprise Services mission critical    
     support teams will recommend implementation of the FIN  (to their  
     respective accounts), at the convenience of the customer. 

iii) For REACTIVE FINs, Enterprise Services will implement the FIN as the   
     need arises.
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