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Asset ID: 1-71-1018072.1
Update Date:2009-11-19
Keywords:

Solution Type  Technical Instruction Sure

Solution  1018072.1 :   Mapping and disabling cores/threads on the Sun Fire[TM] T1000/T2000  


Related Items
  • Sun Fire T2000 Server
  •  
  • Sun Fire T1000 Server
  •  
Related Categories
  • GCS>Sun Microsystems>Servers>CMT Servers
  •  

PreviouslyPublishedAs
229383


Description
The Sun Fire[TM] T1000 and T2000 servers are using the UltraSPARC[R] T1 CMT (Chip Multi Threading) processor, the first SPARC processor with hardware mutithreading.

This document provides the core-to-threads mapping on Sun Fire T1000/T2000 and also the commands to disable and enable cores and threads.



Steps to Follow
The UltraSPARC[R] T1 (Niagara) is a multithreaded processor with 8 cores and 4 threads per core (4-way multithreading) for a maximum of 32 simultaneous threads:

- The 8 cores represent eight integer execution units (pipelines).
- The 4 hardware threads share one pipeline.
- Processor hardware determines hardware thread scheduling.
- Software threads are mapped onto hardware threads by the kernel.

The hardware threads are treated like "CPUs" by the Operating System Scheduler.
The user can see the list of all available cpu threads from both Solaris[TM] (prtdiag -v) and ALOM (showcomponent).

Here is the mapping between the cores and the CPU threads (based on prtdiag -v output from T2000):

        Location        CPU  Freq     Implementation
-------------------------------------------------------
Core 0: MB/CMP0/P0       0   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P1       1   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P2       2   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P3       3   1200 MHz  SUNW,UltraSPARC-T1        
Core 1: MB/CMP0/P4       4   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P5       5   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P6       6   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P7       7   1200 MHz  SUNW,UltraSPARC-T1        
Core 2: MB/CMP0/P8       8   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P9       9   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P10     10   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P11     11   1200 MHz  SUNW,UltraSPARC-T1        
Core 3: MB/CMP0/P12     12   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P13     13   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P14     14   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P15     15   1200 MHz  SUNW,UltraSPARC-T1        
Core 4: MB/CMP0/P16     16   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P17     17   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P18     18   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P19     19   1200 MHz  SUNW,UltraSPARC-T1        
Core 5: MB/CMP0/P20     20   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P21     21   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P22     22   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P23     23   1200 MHz  SUNW,UltraSPARC-T1        
Core 6: MB/CMP0/P24     24   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P25     25   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P26     26   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P27     27   1200 MHz  SUNW,UltraSPARC-T1        
Core 7: MB/CMP0/P28     28   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P29     29   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P30     30   1200 MHz  SUNW,UltraSPARC-T1
MB/CMP0/P31     31   1200 MHz  SUNW,UltraSPARC-T1   

For reference, here is the core-to-thread mapping based on 'showcomponent'

sc> showcomponent
Keys:
MB/CMP0/P0  <--- Core 0
MB/CMP0/P1
MB/CMP0/P2
MB/CMP0/P3 
   MB/CMP0/P4  <--- Core 1
MB/CMP0/P5
MB/CMP0/P6
MB/CMP0/P7 
   MB/CMP0/P8  <--- Core 2
MB/CMP0/P9
MB/CMP0/P10
MB/CMP0/P11 
   MB/CMP0/P12 <--- Core 3
MB/CMP0/P13
MB/CMP0/P14
MB/CMP0/P15 
   MB/CMP0/P16 <--- Core 4
MB/CMP0/P17
MB/CMP0/P18
MB/CMP0/P19 
   MB/CMP0/P20 <--- Core 5
MB/CMP0/P21
MB/CMP0/P22
MB/CMP0/P23 
   MB/CMP0/P24 <--- Core 6
MB/CMP0/P25
MB/CMP0/P26
MB/CMP0/P27 
   MB/CMP0/P28 <--- Core 7
MB/CMP0/P29
MB/CMP0/P30
MB/CMP0/P31 

The cpu threads can be viewed with the ALOM command 'showcomponent' and disabled with the ALOM command 'disablecomponent' (the example is from T2000):

sc> disablecomponent MB/CMP0/P31
sc> showcomponent
Keys:
MB/CMP0/P0
MB/CMP0/P1
MB/CMP0/P2
MB/CMP0/P3
MB/CMP0/P4
MB/CMP0/P5
MB/CMP0/P6
MB/CMP0/P7
MB/CMP0/P8
MB/CMP0/P9
MB/CMP0/P10
MB/CMP0/P11
MB/CMP0/P12
MB/CMP0/P13
MB/CMP0/P14
MB/CMP0/P15
MB/CMP0/P16
MB/CMP0/P17
MB/CMP0/P18
MB/CMP0/P19
MB/CMP0/P20
MB/CMP0/P21
MB/CMP0/P22
MB/CMP0/P23
MB/CMP0/P24
MB/CMP0/P25
MB/CMP0/P26
MB/CMP0/P27
MB/CMP0/P28
MB/CMP0/P29
MB/CMP0/P30
MB/CMP0/P31
MB/CMP0/CH0/R0/D0
MB/CMP0/CH0/R0/D1
MB/CMP0/CH0/R1/D0
MB/CMP0/CH0/R1/D1
MB/CMP0/CH1/R0/D0
MB/CMP0/CH1/R0/D1
MB/CMP0/CH1/R1/D0
MB/CMP0/CH1/R1/D1
MB/CMP0/CH2/R0/D0
MB/CMP0/CH2/R0/D1
MB/CMP0/CH2/R1/D0
MB/CMP0/CH2/R1/D1
MB/CMP0/CH3/R0/D0
MB/CMP0/CH3/R0/D1
MB/CMP0/CH3/R1/D0
MB/CMP0/CH3/R1/D1
IOBD/PCIEa
IOBD/PCIEb
PCIX1
PCIX0
PCIE2
PCIE1
PCIE0
IOBD/USB0
IOBD/USB1
IOBD/USB2
IOBD/USB3
DVD
TTYA
IOBD/NET0
IOBD/NET1
IOBD/NET2
IOBD/NET3 
Disabled Devices
MB/CMP0/P31          : Disabled by user
sc>
SC Alert: MB/CMP0/P31 deemed faulty and disabled
sc>

If the system is powered-off at the time of disabling the thread MB/CMP0/P31 and powered-on afterwards, the disabled cpu thread will be off-lined and then, when the system boots, will be removed from the 'prtdiag -v' and 'psrinfo' list.

If the system is up and running at the time of disabling the thread MB/CMP0/P31 'prtdiag -v' (and psrinfo) will still show this thread as present. After a system reboot the MB/CMP0/P31 will no longer be in the 'prtdiag -v' and 'psrinfo' output.

The thread can be re-enabled by 'enablecomponent':

sc> enablecomponent MB/CMP0/P31
sc> showcomponent
Keys:
MB/CMP0/P0
MB/CMP0/P1
MB/CMP0/P2
MB/CMP0/P3
MB/CMP0/P4
MB/CMP0/P5
MB/CMP0/P6
MB/CMP0/P7
MB/CMP0/P8
MB/CMP0/P9
MB/CMP0/P10
MB/CMP0/P11
MB/CMP0/P12
MB/CMP0/P13
MB/CMP0/P14
MB/CMP0/P15
MB/CMP0/P16
MB/CMP0/P17
MB/CMP0/P18
MB/CMP0/P19
MB/CMP0/P20
MB/CMP0/P21
MB/CMP0/P22
MB/CMP0/P23
MB/CMP0/P24
MB/CMP0/P25
MB/CMP0/P26
MB/CMP0/P27
MB/CMP0/P28
MB/CMP0/P29
MB/CMP0/P30
MB/CMP0/P31
MB/CMP0/CH0/R0/D0
MB/CMP0/CH0/R0/D1
MB/CMP0/CH0/R1/D0
MB/CMP0/CH0/R1/D1
MB/CMP0/CH1/R0/D0
MB/CMP0/CH1/R0/D1
MB/CMP0/CH1/R1/D0
MB/CMP0/CH1/R1/D1
MB/CMP0/CH2/R0/D0
MB/CMP0/CH2/R0/D1
MB/CMP0/CH2/R1/D0
MB/CMP0/CH2/R1/D1
MB/CMP0/CH3/R0/D0
MB/CMP0/CH3/R0/D1
MB/CMP0/CH3/R1/D0
MB/CMP0/CH3/R1/D1
IOBD/PCIEa
IOBD/PCIEb
PCIX1
PCIX0
PCIE2
PCIE1
PCIE0
IOBD/USB0
IOBD/USB1
IOBD/USB2
IOBD/USB3
DVD
TTYA
IOBD/NET0
IOBD/NET1
IOBD/NET2
IOBD/NET3 
State: Clean
SC Alert: MB/CMP0/P31 reenabled

An idle or disabled cpu thread doesn't mean that the entire core is idle or disabled. To disable a core you will need to disable all four hardware threads associated with that core. Here is an example for core 7:

sc> disablecomponent MB/CMP0/P28
sc> disablecomponent MB/CMP0/P29
sc> disablecomponent MB/CMP0/P30
sc> disablecomponent MB/CMP0/P31
sc>
SC Alert: MB/CMP0/P28 deemed faulty and disabled
SC Alert: MB/CMP0/P29 deemed faulty and disabled
SC Alert: MB/CMP0/P30 deemed faulty and disabled
SC Alert: MB/CMP0/P31 deemed faulty and disabled
sc> showcomponent
Keys:
MB/CMP0/P0
MB/CMP0/P1
MB/CMP0/P2
MB/CMP0/P3
MB/CMP0/P4
MB/CMP0/P5
MB/CMP0/P6
MB/CMP0/P7
MB/CMP0/P8
MB/CMP0/P9
MB/CMP0/P10
MB/CMP0/P11
MB/CMP0/P12
MB/CMP0/P13
MB/CMP0/P14
MB/CMP0/P15
MB/CMP0/P16
MB/CMP0/P17
MB/CMP0/P18
MB/CMP0/P19
MB/CMP0/P20
MB/CMP0/P21
MB/CMP0/P22
MB/CMP0/P23
MB/CMP0/P24
MB/CMP0/P25
MB/CMP0/P26
MB/CMP0/P27
MB/CMP0/P28
MB/CMP0/P29
MB/CMP0/P30
MB/CMP0/P31
................
Disabled Devices
MB/CMP0/P28          : Disabled by user
MB/CMP0/P29          : Disabled by user
MB/CMP0/P30          : Disabled by user
MB/CMP0/P31          : Disabled by user
sc> 

To enable core 7 you'll need to re-enable all 4 threads and then reboot.

Note: the command 'psradm -f cpu#' can also be used to take cpu threads/cores off-line, but this will be for OS purposes only and the OS (Solaris) will not use the off-lined cpu. The cpu thread/core will be reported off-line in the psrinfo output, however it will be physically present and will be displayed in the 'prtdiag -v' output.

The disabled thread will come back online after a system reboot or after beeing re-enabled with 'psradm -n cpu#'.



Product
Sun Fire T1000 Server
Sun Fire T2000 Server

T1000, T2000, core, thread, mapping, disablecomponent, enablecomponent
Previously Published As
85929

Change History
Date: 2009-11-19
User Name: Anthony Rulli
Action: Updated
Comment: currency check, audited by Anthony Rulli, Entry Level SPARC Content team
Spell cke OK.
Trademarks added.
OK to publish.
Version: 3

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